Domain-specific Hardware Accelerators

Programmable Accelerators for Lattice-based Public Key Protocols

Post Quantum Lattice-Based Cryptography (LBC) schemes are increasingly gaining attention in traditional and emerging security problems, such as encryption, digital signature, key exchange, homomorphic encryption etc, to address security needs of both short and long-lived devices — due to their foundational properties and ease of implementation. However, LBC schemes induce higher computational demand compared to classic schemes (e.g., DSA, ECDSA) for equivalent security guarantees, making domain-specific acceleration a viable option for improving security and favor early adoption of LBC schemes by the semiconductor industry.

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Scale Down Neural Network Models Considering HW Constraints

Traditionally machine learning (ML) computations have been performed on resourceful servers due to the high computational demands of these ML techniques. However, when these ML techniques are deployed for emerging applications that are heavily resource-constrained (e.g., smartphones, mobile platforms, IoT devices), time-critical (e.g., self-driving cars), or in environments where cloud connectivity is not reliably available, there is a need to perform ML computation/acceleration on the device itself. Furthermore, consumers are increasingly concerned about the privacy of their data when stored on public clouds.  All of these concerns pose daunting challenges for ML formulations and on-device acceleration.  On one hand, due to the limited resources, on-device AI should scale-down the network models (e.g. changing the number of layers, neurons per layer, etc.).  On the other hand, on-device AI acceleration must simultaneously satisfy multiple constraints including power consumption, latency, privacy and accuracy of the prediction.

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Publications

2019

Peroni, Daniel; Imani, Mohsen; Hamid, Nejatollahi; Dutt, Nikil; Rosing, Tajana

ARGA: Approximate Reuse for GPGPU Acceleration Conference

IEEE/ACM Design Automation Conference (DAC), 2019.

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Seto, Kenshu; Nejatollahi, Hamid; An, Jiyoung; Kang, Sujin; Dutt, Nikil

Small Memory Footprint Neural Network Accelerators Inproceedings

International Symposium on Quality Electronic Design (ISQED), 2019.

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Nejatollahi, Hamid ; Dutt, Nikil ; Ray, Sandip ; Regazzoni, Francesco ; Banerjee, Indranil ; Cammarota, Rosario

Post-Quantum Lattice-Based Cryptography Implementations: A Survey Journal Article

ACM Computing Survey, 51 (6), 2019, ISSN: 0360-0300.

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2018

Nejatollahi, Hamid; Dutt, Nikil; Banerjee, Indranil; Cammarota, Rosario

Domain-specific Accelerators for Ideal Lattice-based Public Key Protocols Miscellaneous

Cryptology ePrint Archive, Report 2018/608, 2018, (urlhttps://eprint.iacr.org/2018/608).

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2017

Nejatollahi, Hamid; Dutt, Nikil; Cammarota, Rosario

Trends, Challenges and Needs for Lattice-based Cryptography Implementations: Special Session Inproceedings

Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, pp. 6:1–6:3, ACM, Seoul, Republic of Korea, 2017, ISBN: 978-1-4503-5185-0.

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Nejatollahi, Hamid; Dutt, Nikil; Ray, Sandip; Regazzoni, Francesco; Banerjee, Indranil; Cammarota, Rosario

Software and Hardware Implementation of Lattice-Cased Cryptography Schemes Technical Report

University of California Irvine, (CECS TR 17-04), 2017.

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