The project introduces the notion of a self-aware Information Processing Factory (IPF) as a step towards autonomous Multi-Processor System-on-Chip (MPSoC) platforms in Cyber-Physical Systems (CPS) and the Internet of Things (IoT). IPF represents a paradigm shift in platform design, with robust and independent platform operation focusing on futuristic platform-centric design, rather than the traditional focus on semiconductor devices and software technology. Emerging CPS and IoT application domains exhibit several-orders-of-magnitude increase in complexity, both in the number of objects, as well as in their dynamic and unpredictable interactions. Systems are increasingly becoming autonomous and demand a radically new strategy to conquer and control this runaway complexity. The project exploits self-awareness principles, together with lessons learned from large-scale factories to contain complexity, achieve predictability and manage robust system design. The overall research theme will demonstrate the utility of self-aware IPFs in managing MPSoC complexity, while achieving scalability, predictability, and system efficiency, with the long term goal of supporting autonomous systems as a main application.
IPF project is an international collaboration among the following universities:
SPECTR: Supervisory Control for Many-core Systems Resource Management
Resource management strategies for many-core systems need to enable sharing of resources such as power, processing cores, and memory bandwidth while coordinating the priority and signifcance of system- and application-level objectives at runtime in a scalable and robust manner. State-of-the-art approaches use heuristics or machine learning for resource management, but unfortunately lack formalism in providing robustness against unexpected corner cases. While recent eﬀorts deploy classical control-theoretic approaches with some guarantees and formalism, they lack scalability and autonomy to meet changing runtime goals.
We present SPECTR, a new resource management approach for many-core systems that leverages formal supervisory control theory (SCT) to combine the strengths of classical control theory with state-of-the-art heuristic approaches to efciently meet changing runtime goals. SPECTR is a scalable and robust control architecture and a systematic design ﬂow for hierarchical control of many-core systems. SPECTR leverages SCT techniques such as gain scheduling to allow autonomy for individual controllers. It facilitates automatic synthesis of the high-level supervisory controller
SPARTA: Runtime Task Allocation for Heterogeneous Many-cores
We present SPARTA, a throughputaware runtime task allocation approach for Heterogeneous
Many-core Platforms (HMPs) to achieve energy efficiency.
SPARTA collects sensor data to characterize tasks at runtime and uses this information to prioritize tasks when performing allocation in order to maximize energy-efficiency (instructions-per-Joule) without sacrificing performance.
Gain Scheduled Control for Nonlinear Power Management
Dynamic voltage and frequency scaling (DVFS) is a well-established technique for power management of thermal- or energy-sensitive chip multiprocessors (CMPs). In this context, linear control theoretic solutions have been successfully implemented to control the voltage-frequency knobs. However, modern CMPs with a large range of operating frequencies and multiple voltage levels display nonlinear behavior in the relationship between frequency and power. State-of-the-art linear controllers therefore under-optimize DVFS operation.
We propose a Gain Scheduled Controller (GSC) for nonlinear runtime power management of CMPs that simplifies the controller implementation of systems with varying dynamic properties by utilizing an adaptive control theoretic approach in conjunction with static linear controllers. Our design improves the accuracy of the controller over a static linear controller with minimal overhead.
Trends in On-chip Dynamic Resource Management Inproceedings
2018 21st Euromicro Conference on Digital System Design (DSD), pp. 62-69, 2018.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, New York, NY, USA, 2018, ISBN: 978-1-4503-4911-6.
2018 Design, Automation Test in Europe Conference Exhibition (DATE), 2018.
2018 Design, Automation Test in Europe Conference Exhibition (DATE), 2018, ISSN: 1558-1101.
Guest Editorial: Special Issue on Self-Aware Systems on Chip Journal Article
IEEE Design & Test, 34 (6), pp. 6–7, 2017.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES 2016, Pittsburgh, Pennsylvania, USA, October 1-7, 2016, pp. 27:1–27:10, 2016.