2019
|
Peroni, Daniel; Imani, Mohsen; Hamid, Nejatollahi; Dutt, Nikil; Rosing, Tajana ARGA: Approximate Reuse for GPGPU Acceleration Conference Forthcoming IEEE/ACM Design Automation Conference (DAC), Forthcoming. BibTeX @conference{Nejatollahi-dac-2019,
title = {ARGA: Approximate Reuse for GPGPU Acceleration},
author = {Daniel Peroni and Mohsen Imani and Nejatollahi Hamid and Nikil Dutt and Tajana Rosing},
year = {2019},
date = {2019-05-01},
booktitle = { IEEE/ACM Design Automation Conference (DAC)},
keywords = {},
pubstate = {forthcoming},
tppubtype = {conference}
}
|
Seto, Kenshu; Nejatollahi, Hamid; An, Jiyoung; Kang, Sujin; Dutt, Nikil Small Memory Footprint Neural Network Accelerators Inproceedings Forthcoming International Symposium on Quality Electronic Design (ISQED), Forthcoming. BibTeX @inproceedings{000b,
title = {Small Memory Footprint Neural Network Accelerators},
author = {Kenshu Seto and Hamid Nejatollahi and Jiyoung An and Sujin Kang and Nikil Dutt},
year = {2019},
date = {2019-03-01},
booktitle = {International Symposium on Quality Electronic Design (ISQED)},
keywords = {},
pubstate = {forthcoming},
tppubtype = {inproceedings}
}
|
Nejatollahi, Hamid ; Dutt, Nikil ; Ray, Sandip ; Regazzoni, Francesco ; Banerjee, Indranil ; Cammarota, Rosario Post-Quantum Lattice-Based Cryptography Implementations: A Survey Journal Article ACM Computing Survey, 51 (6), 2019, ISSN: 0360-0300. Abstract | Links | BibTeX @article{Nejatollahi2019,
title = {Post-Quantum Lattice-Based Cryptography Implementations: A Survey},
author = {Nejatollahi, Hamid and Dutt, Nikil and Ray, Sandip and Regazzoni, Francesco and Banerjee, Indranil and Cammarota, Rosario},
doi = {10.1145/3292548},
issn = {0360-0300},
year = {2019},
date = {2019-01-04},
journal = {ACM Computing Survey},
volume = {51},
number = {6},
abstract = {The advent of quantum computing threatens to break many classical cryptographic schemes, leading to innovations in public key cryptography that focus on post-quantum cryptography primitives and protocols resistant to quantum computing threats. Lattice-based cryptography is a promising post-quantum cryptography family, both in terms of foundational properties as well as in its application to both traditional and emerging security problems such as encryption, digital signature, key exchange, and homomorphic encryption. While such techniques provide guarantees, in theory, their realization on contemporary computing platforms requires careful design choices and tradeoffs to manage both the diversity of computing platforms (e.g., high-performance to resource constrained), as well as the agility for deployment in the face of emerging and changing standards. In this work, we survey trends in lattice-based cryptographic schemes, some recent fundamental proposals for the use of lattices in computer security, challenges for their implementation in software and hardware, and emerging needs for their adoption. The survey means to be informative about the math to allow the reader to focus on the mechanics of the computation ultimately needed for mapping schemes on existing hardware or synthesizing part or all of a scheme on special-purpose hardware.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
The advent of quantum computing threatens to break many classical cryptographic schemes, leading to innovations in public key cryptography that focus on post-quantum cryptography primitives and protocols resistant to quantum computing threats. Lattice-based cryptography is a promising post-quantum cryptography family, both in terms of foundational properties as well as in its application to both traditional and emerging security problems such as encryption, digital signature, key exchange, and homomorphic encryption. While such techniques provide guarantees, in theory, their realization on contemporary computing platforms requires careful design choices and tradeoffs to manage both the diversity of computing platforms (e.g., high-performance to resource constrained), as well as the agility for deployment in the face of emerging and changing standards. In this work, we survey trends in lattice-based cryptographic schemes, some recent fundamental proposals for the use of lattices in computer security, challenges for their implementation in software and hardware, and emerging needs for their adoption. The survey means to be informative about the math to allow the reader to focus on the mechanics of the computation ultimately needed for mapping schemes on existing hardware or synthesizing part or all of a scheme on special-purpose hardware. |
2018
|
Amiri, Delaram; Anzanpour, Arman; Azimi, Iman; Levorato, Marco; Rahmani, Amir M; Liljeberg, Pasi; Dutt, Nikil Edge-Assisted Sensor Control in Healthcare IoT Inproceedings 2018 IEEE Global Communications Conference (GLOBECOM), pp. 1–6, 2018. Abstract | Links | BibTeX @inproceedings{amiri2018edge,
title = {Edge-Assisted Sensor Control in Healthcare IoT},
author = {Delaram Amiri and Arman Anzanpour and Iman Azimi and Marco Levorato and Amir M. Rahmani and Pasi Liljeberg and Nikil Dutt},
doi = {10.1109/GLOCOM.2018.8647457},
year = {2018},
date = {2018-12-09},
booktitle = {2018 IEEE Global Communications Conference (GLOBECOM)},
pages = {1--6},
abstract = {The Internet of Things is a key enabler of mobile health-care applications. However, the inherent constraints of mobile devices, such as limited availability of energy, can impair their ability to produce accurate data and, in turn, degrade the output of algorithms processing them in real-time to evaluate the patient’s state. This paper presents an edge-assisted framework, where models and control generated by an edge server inform the sensing parameters of mobile sensors. The objective is to maximize the probability that anomalies in the collected signals are detected over extensive periods of time under batteryimposed constraints. Although the proposed concept is general, the control framework is made specific to a use-case where vital signs – heart rate, respiration rate and oxygen saturation – are extracted from a Photoplethysmogram (PPG) signal to detect anomalies in real-time. Experimental results show a 16.9% reduction in sensing energy consumption in comparison to a constant energy consumption with the maximum misdetection probability of 0.17 in a 24-hour health monitoring system.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
The Internet of Things is a key enabler of mobile health-care applications. However, the inherent constraints of mobile devices, such as limited availability of energy, can impair their ability to produce accurate data and, in turn, degrade the output of algorithms processing them in real-time to evaluate the patient’s state. This paper presents an edge-assisted framework, where models and control generated by an edge server inform the sensing parameters of mobile sensors. The objective is to maximize the probability that anomalies in the collected signals are detected over extensive periods of time under batteryimposed constraints. Although the proposed concept is general, the control framework is made specific to a use-case where vital signs – heart rate, respiration rate and oxygen saturation – are extracted from a Photoplethysmogram (PPG) signal to detect anomalies in real-time. Experimental results show a 16.9% reduction in sensing energy consumption in comparison to a constant energy consumption with the maximum misdetection probability of 0.17 in a 24-hour health monitoring system. |
Hsieh, Chenying; Dutt, Nikil; Sani, Ardalan The Case for Exploiting Underutilized Resources in Heterogeneous Mobile Architectures Conference Forthcoming Forthcoming. Abstract | BibTeX @conference{Hsieh2018,
title = {The Case for Exploiting Underutilized Resources in Heterogeneous Mobile Architectures},
author = {Chenying Hsieh and Nikil Dutt and Ardalan Sani},
year = {2018},
date = {2018-11-08},
abstract = {Heterogeneous architectures are ubiquitous in mobile platforms, with mobile SoCs typically integrating multiple processors along with accelerators such as GPUs (for data parallel kernels) and DSPs (for signal processing kernels). This strict partitioning of application execution on heterogeneous compute resources often results in underutilization of resources such as DSPs. We present a case study executing a mix of popular data-parallel workloads such as convolutional neural networks (CNNs), computer vision filters and graphics rendering kernels on mobile devices, and show that both performance and energy consumption of mobile platforms can be improved by synergistically deploying these underutilized compute resources. Our experiments on a mobile Snapdragon 835 platform under both single and multiple application scenarios executing the aforementioned workloads demonstrates average performance and energy improvements of 15-46% and 18-80%, respectively, by synergistically deploying all available compute resources, especially the underutilized DSP. These studies make a strong case for developing a unified runtime system that can better exploit underutilized resources in the face of increasing accelerator diversity in heterogeneous mobile platforms.
},
keywords = {},
pubstate = {forthcoming},
tppubtype = {conference}
}
Heterogeneous architectures are ubiquitous in mobile platforms, with mobile SoCs typically integrating multiple processors along with accelerators such as GPUs (for data parallel kernels) and DSPs (for signal processing kernels). This strict partitioning of application execution on heterogeneous compute resources often results in underutilization of resources such as DSPs. We present a case study executing a mix of popular data-parallel workloads such as convolutional neural networks (CNNs), computer vision filters and graphics rendering kernels on mobile devices, and show that both performance and energy consumption of mobile platforms can be improved by synergistically deploying these underutilized compute resources. Our experiments on a mobile Snapdragon 835 platform under both single and multiple application scenarios executing the aforementioned workloads demonstrates average performance and energy improvements of 15-46% and 18-80%, respectively, by synergistically deploying all available compute resources, especially the underutilized DSP. These studies make a strong case for developing a unified runtime system that can better exploit underutilized resources in the face of increasing accelerator diversity in heterogeneous mobile platforms.
|
Moazzemi, K; Kanduri, A; Juhász, D; Miele, A; Rahmani, A M; Liljeberg, P; Jantsch, A; Dutt, N Trends in On-chip Dynamic Resource Management Inproceedings 2018 21st Euromicro Conference on Digital System Design (DSD), pp. 62-69, 2018. Links | BibTeX @inproceedings{8491796,
title = {Trends in On-chip Dynamic Resource Management},
author = {K Moazzemi and A Kanduri and D Juhász and A Miele and A M Rahmani and P Liljeberg and A Jantsch and N Dutt},
doi = {10.1109/DSD.2018.00025},
year = {2018},
date = {2018-08-01},
booktitle = {2018 21st Euromicro Conference on Digital System Design (DSD)},
pages = {62-69},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Donvanavard, B; Monazzah, A M H; Dutt, N; Mück, T Exploring Hybrid Memory Caches in Chip Multiprocessors Inproceedings 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-8, 2018. Links | BibTeX @inproceedings{8449386,
title = {Exploring Hybrid Memory Caches in Chip Multiprocessors},
author = {B Donvanavard and A M H Monazzah and N Dutt and T Mück},
doi = {10.1109/ReCoSoC.2018.8449386},
year = {2018},
date = {2018-07-01},
booktitle = {2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)},
pages = {1-8},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Rahmani, Amir M; Donyanavard, Bryan; Mück, Tiago; Moazzemi, Kasra; Jantsch, Axel; Mutlu, Onur; Dutt, Nikil SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management Conference Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, New York, NY, USA, 2018, ISBN: 978-1-4503-4911-6. Abstract | Links | BibTeX @conference{Rahmani:2018:SFS:3173162.3173199,
title = {SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management},
author = {Amir M. Rahmani and Bryan Donyanavard and Tiago Mück and Kasra Moazzemi and Axel Jantsch and Onur Mutlu and Nikil Dutt},
url = {http://doi.acm.org/10.1145/3173162.3173199, ACM
http://duttgroup.ics.uci.edu/wp-content/drg/uploads/2018/05/SPECTR-formal-supervisory-control-for-many-core-resource-management_asplos18-lightning-talk.pptx, Lightning Talk [pptx]
http://duttgroup.ics.uci.edu/wp-content/drg/uploads/2018/05/SPECTR-formal-supervisory-control-for-many-core-resource-management_asplos18-lightning-talk.pdf, Lightning Talk [pdf]
http://duttgroup.ics.uci.edu/wp-content/drg/uploads/2018/05/SPECTR-formal-supervisory-control-for-many-core-resource-management_asplos18-talk.pptx, Slides [pptx]
http://duttgroup.ics.uci.edu/wp-content/drg/uploads/2018/05/SPECTR-formal-supervisory-control-for-many-core-resource-management_asplos18-talk.pdf, Slides [pdf]
http://duttgroup.ics.uci.edu/wp-content/drg/uploads/2018/05/SPECTR-formal-supervisory-control-for-many-core-resource-management_asplos18-poster.pptx, Poster [pptx]
http://duttgroup.ics.uci.edu/wp-content/drg/uploads/2018/05/SPECTR-formal-supervisory-control-for-many-core-resource-management_asplos18-poster.pdf, Poster [pdf]
},
doi = {10.1145/3173162.3173199},
isbn = {978-1-4503-4911-6},
year = {2018},
date = {2018-03-27},
booktitle = {Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems},
pages = {169--183},
publisher = {ACM},
address = {New York, NY, USA},
abstract = {Resource management strategies for many-core systems need to enable sharing of resources such as power, processing cores, and memory bandwidth while coordinating the priority and significance of system- and application-level objectives at runtime in a scalable and robust manner. State-of-the-art approaches use heuristics or machine learning for resource management, but unfortunately lack formalism in providing robustness against unexpected corner cases. While recent efforts deploy classical control-theoretic approaches with some guarantees and formalism, they lack scalability and autonomy to meet changing runtime goals. We present SPECTR, a new resource management approach for many-core systems that leverages formal supervisory control theory (SCT) to combine the strengths of classical control theory with state-of-the-art heuristic approaches to efficiently meet changing runtime goals. SPECTR is a scalable and robust control architecture and a systematic design flow for hierarchical control of many-core systems. SPECTR leverages SCT techniques such as gain scheduling to allow autonomy for individual controllers. It facilitates automatic synthesis of the high-level supervisory controller and its property verification. We implement SPECTR on an Exynos platform containing ARM's big.LITTLE-based heterogeneous multi-processor (HMP) and demonstrate that SPECTR»s use of SCT is key to managing multiple interacting resources (e.g., chip power and processing cores) in the presence of competing objectives (e.g., satisfying QoS vs. power capping). The principles of SPECTR are easily applicable to any resource type and objective as long as the management problem can be modeled using dynamical systems theory (e.g., difference equations), discrete-event dynamic systems, or fuzzy dynamics.
},
keywords = {},
pubstate = {published},
tppubtype = {conference}
}
Resource management strategies for many-core systems need to enable sharing of resources such as power, processing cores, and memory bandwidth while coordinating the priority and significance of system- and application-level objectives at runtime in a scalable and robust manner. State-of-the-art approaches use heuristics or machine learning for resource management, but unfortunately lack formalism in providing robustness against unexpected corner cases. While recent efforts deploy classical control-theoretic approaches with some guarantees and formalism, they lack scalability and autonomy to meet changing runtime goals. We present SPECTR, a new resource management approach for many-core systems that leverages formal supervisory control theory (SCT) to combine the strengths of classical control theory with state-of-the-art heuristic approaches to efficiently meet changing runtime goals. SPECTR is a scalable and robust control architecture and a systematic design flow for hierarchical control of many-core systems. SPECTR leverages SCT techniques such as gain scheduling to allow autonomy for individual controllers. It facilitates automatic synthesis of the high-level supervisory controller and its property verification. We implement SPECTR on an Exynos platform containing ARM's big.LITTLE-based heterogeneous multi-processor (HMP) and demonstrate that SPECTR»s use of SCT is key to managing multiple interacting resources (e.g., chip power and processing cores) in the presence of competing objectives (e.g., satisfying QoS vs. power capping). The principles of SPECTR are easily applicable to any resource type and objective as long as the management problem can be modeled using dynamical systems theory (e.g., difference equations), discrete-event dynamic systems, or fuzzy dynamics.
|
Donyanavard, Bryan; Rahmani, Amir M; Mück, Tiago; Moazzemi, Kasra; Dutt, Nikil Gain Scheduled Control for Nonlinear Power Management in CMPs Conference 2018 Design, Automation Test in Europe Conference Exhibition (DATE), 2018. Abstract | Links | BibTeX @conference{8342141,
title = {Gain Scheduled Control for Nonlinear Power Management in CMPs},
author = {Bryan Donyanavard and Amir M. Rahmani and Tiago Mück and Kasra Moazzemi and Nikil Dutt},
url = {https://doi.org/10.23919/DATE.2018.8342141},
doi = {10.23919/DATE.2018.8342141},
year = {2018},
date = {2018-03-19},
booktitle = {2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
pages = {921-924},
abstract = {Dynamic voltage and frequency scaling (DVFS) is a well-established technique for power management of thermal-or energy-sensitive chip multiprocessors (CMPs). In this context, linear control theoretic solutions have been successfully implemented to control the voltage-frequency knobs. However, modern CMPs with a large range of operating frequencies and multiple voltage levels display nonlinear behavior in the relationship between frequency and power. State-of-the-art linear controllers therefore under-optimize DVFS operation. We propose a Gain Scheduled Controller (GSC) for nonlinear runtime power management of CMPs that simplifies the controller implementation of systems with varying dynamic properties by utilizing an adaptive control theoretic approach in conjunction with static linear controllers. Our design improves the accuracy of the controller over a static linear controller with minimal overhead. We implement our approach on an Exynos platform containing ARM's big.LITTLE-based heterogeneous multi-processor (HMP) and demonstrate that the system's response to changes in target power is improved by 2x while operating up to 12% more efficiently for tracking accuracy.},
keywords = {},
pubstate = {published},
tppubtype = {conference}
}
Dynamic voltage and frequency scaling (DVFS) is a well-established technique for power management of thermal-or energy-sensitive chip multiprocessors (CMPs). In this context, linear control theoretic solutions have been successfully implemented to control the voltage-frequency knobs. However, modern CMPs with a large range of operating frequencies and multiple voltage levels display nonlinear behavior in the relationship between frequency and power. State-of-the-art linear controllers therefore under-optimize DVFS operation. We propose a Gain Scheduled Controller (GSC) for nonlinear runtime power management of CMPs that simplifies the controller implementation of systems with varying dynamic properties by utilizing an adaptive control theoretic approach in conjunction with static linear controllers. Our design improves the accuracy of the controller over a static linear controller with minimal overhead. We implement our approach on an Exynos platform containing ARM's big.LITTLE-based heterogeneous multi-processor (HMP) and demonstrate that the system's response to changes in target power is improved by 2x while operating up to 12% more efficiently for tracking accuracy. |
Sagdighi, Armin; Donyanavard, Bryan; Kadeed, Thawra; Moazzemi, Kasra; Mück, Tiago; Nassar, Ahmed; Rahmani, Amir M; Wild, Thomas; Dutt, Nikil; Ernst, Rolf; Herkersdorf, Andreas; Kurdahi, Fadi Design Methodologies for Enabling Self-awareness in Autonomous Systems Conference 2018 Design, Automation Test in Europe Conference Exhibition (DATE), 2018, ISSN: 1558-1101. Abstract | Links | BibTeX @conference{8342259,
title = {Design Methodologies for Enabling Self-awareness in Autonomous Systems},
author = {Armin Sagdighi and Bryan Donyanavard and Thawra Kadeed and Kasra Moazzemi and Tiago Mück and Ahmed Nassar and Amir M. Rahmani and Thomas Wild and Nikil Dutt and Rolf Ernst and Andreas Herkersdorf and Fadi Kurdahi},
url = {https://doi.org/10.23919/DATE.2018.8342259},
doi = {10.23919/DATE.2018.8342259},
issn = {1558-1101},
year = {2018},
date = {2018-03-19},
booktitle = {2018 Design, Automation Test in Europe Conference Exhibition (DATE)},
pages = {1532-1537},
abstract = {This paper deals with challenges and possible solutions for incorporating self-awareness principles in EDA design flows for autonomous systems. We present a holistic approach that enables self-awareness across the software/hardware stack, from systems-on-chip to systems-of-systems (autonomous car) contexts. We use the Information Processing Factory (IPF) metaphor as an exemplar to show how self-awareness can be achieved across multiple abstraction levels, and discuss new research challenges. The IPF approach represents a paradigm shift in platform design by envisioning the move towards a consequent platform-centric design in which the combination of self-organizing learning and formal reactive methods guarantee the applicability of such cyber-physical systems in safety-critical and high-availability applications.
},
keywords = {},
pubstate = {published},
tppubtype = {conference}
}
This paper deals with challenges and possible solutions for incorporating self-awareness principles in EDA design flows for autonomous systems. We present a holistic approach that enables self-awareness across the software/hardware stack, from systems-on-chip to systems-of-systems (autonomous car) contexts. We use the Information Processing Factory (IPF) metaphor as an exemplar to show how self-awareness can be achieved across multiple abstraction levels, and discuss new research challenges. The IPF approach represents a paradigm shift in platform design by envisioning the move towards a consequent platform-centric design in which the combination of self-organizing learning and formal reactive methods guarantee the applicability of such cyber-physical systems in safety-critical and high-availability applications.
|
Nejatollahi, Hamid; Dutt, Nikil; Banerjee, Indranil; Cammarota, Rosario Domain-specific Accelerators for Ideal Lattice-based Public Key Protocols Miscellaneous Cryptology ePrint Archive, Report 2018/608, 2018, (urlhttps://eprint.iacr.org/2018/608). Abstract | Links | BibTeX @misc{cryptoeprint:2018:608,
title = {Domain-specific Accelerators for Ideal Lattice-based Public Key Protocols},
author = {Hamid Nejatollahi and Nikil Dutt and Indranil Banerjee and Rosario Cammarota},
url = {https://eprint.iacr.org/2018/608.pdf},
year = {2018},
date = {2018-01-01},
abstract = {Post Quantum Lattice-Based Cryptography (LBC) schemes are increasingly gaining attention in traditional and emerging security problems, such as encryption, digital signature, key exchange, homomorphic encryption etc, to address security needs of both short and long-lived devices — due to their foundational properties and ease of implementation. However, LBC schemes induce higher computational demand compared to classic schemes (e.g., DSA, ECDSA) for equivalent security guarantees, making domain-specific acceleration a viable option for improving security and favor early adoption of LBC schemes by the semiconductor industry. In this paper, we present a workflow to explore the design space of domain-specific accelerators for LBC schemes, to target a diverse set of host devices, from resource-constrained IoT devices to high-performance computing platforms. We present design exploration results on workloads executing NewHope and BLISSB-I schemes accelerated by our domain-specific accelerators, with respect to a baseline without acceleration. We show that achieved performance with acceleration makes the execution of NewHope and BLISSB-I comparable to classic key exchange and digital signature schemes while retaining some form of general purpose programmability. In addition to 44% and 67% improvement in energy-delay product (EDP), we enhance performance (cycles) of the sign and verify steps in BLISSB-I schemes by 24% and 47%, respectively. Performance (EDP) improvement of server and client side of the NewHope key exchange is improved by 37% and 33% (52% and 48%), demonstrating the utility of the design space exploration framework.
},
howpublished = {Cryptology ePrint Archive, Report 2018/608},
note = {urlhttps://eprint.iacr.org/2018/608},
keywords = {},
pubstate = {published},
tppubtype = {misc}
}
Post Quantum Lattice-Based Cryptography (LBC) schemes are increasingly gaining attention in traditional and emerging security problems, such as encryption, digital signature, key exchange, homomorphic encryption etc, to address security needs of both short and long-lived devices — due to their foundational properties and ease of implementation. However, LBC schemes induce higher computational demand compared to classic schemes (e.g., DSA, ECDSA) for equivalent security guarantees, making domain-specific acceleration a viable option for improving security and favor early adoption of LBC schemes by the semiconductor industry. In this paper, we present a workflow to explore the design space of domain-specific accelerators for LBC schemes, to target a diverse set of host devices, from resource-constrained IoT devices to high-performance computing platforms. We present design exploration results on workloads executing NewHope and BLISSB-I schemes accelerated by our domain-specific accelerators, with respect to a baseline without acceleration. We show that achieved performance with acceleration makes the execution of NewHope and BLISSB-I comparable to classic key exchange and digital signature schemes while retaining some form of general purpose programmability. In addition to 44% and 67% improvement in energy-delay product (EDP), we enhance performance (cycles) of the sign and verify steps in BLISSB-I schemes by 24% and 47%, respectively. Performance (EDP) improvement of server and client side of the NewHope key exchange is improved by 37% and 33% (52% and 48%), demonstrating the utility of the design space exploration framework.
|
Chou, Ting-Shuo; Kashyap, Hirak J; Xing, Jinwei; Listopad, Stanislav; Rounds, Emily L CARLsim 4: An Open Source Library for Large Scale, Biologically Detailed Spiking Neural Network Simulation using Heterogeneous Clusters Conference International Joint Conference on Neural Networks (IJCNN), 2018. Links | BibTeX @conference{choucarlsim,
title = {CARLsim 4: An Open Source Library for Large Scale, Biologically Detailed Spiking Neural Network Simulation using Heterogeneous Clusters},
author = {Ting-Shuo Chou and Hirak J Kashyap and Jinwei Xing and Stanislav Listopad and Emily L Rounds},
url = {http://www.socsci.uci.edu/~jkrichma/Chou-Kashyap-CARLsim4-IJCNN2018.pdf, paper},
year = {2018},
date = {2018-01-01},
booktitle = {International Joint Conference on Neural Networks (IJCNN)},
keywords = {},
pubstate = {published},
tppubtype = {conference}
}
|
Kashyap, Hirak J; Detorakis, Georgios; Dutt, Nikil; Krichmar, Jeffrey L; Neftci, Emre A Recurrent Neural Network Based Model of Predictive Smooth Pursuit Eye Movement in Primates Conference International Joint Conference on Neural Networks (IJCNN), 2018. Links | BibTeX @conference{kashyaprecurrent,
title = {A Recurrent Neural Network Based Model of Predictive Smooth Pursuit Eye Movement in Primates},
author = {Hirak J Kashyap and Georgios Detorakis and Nikil Dutt and Jeffrey L Krichmar and Emre Neftci},
url = {http://www.socsci.uci.edu/~jkrichma/Kashyap-PredicitvePursuit-IJCNN2018.pdf, paper},
year = {2018},
date = {2018-01-01},
booktitle = {International Joint Conference on Neural Networks (IJCNN)},
keywords = {},
pubstate = {published},
tppubtype = {conference}
}
|
2017
|
Nejatollahi, Hamid; Dutt, Nikil; Cammarota, Rosario Trends, Challenges and Needs for Lattice-based Cryptography Implementations: Special Session Inproceedings Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, pp. 6:1–6:3, ACM, Seoul, Republic of Korea, 2017, ISBN: 978-1-4503-5185-0. Links | BibTeX @inproceedings{Nejatollahi:2017:TCN:3125502.3125559,
title = {Trends, Challenges and Needs for Lattice-based Cryptography Implementations: Special Session},
author = {Hamid Nejatollahi and Nikil Dutt and Rosario Cammarota},
url = {http://doi.acm.org/10.1145/3125502.3125559},
doi = {10.1145/3125502.3125559},
isbn = {978-1-4503-5185-0},
year = {2017},
date = {2017-10-15},
booktitle = {Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion},
pages = {6:1--6:3},
publisher = {ACM},
address = {Seoul, Republic of Korea},
series = {CODES '17},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Nejatollahi, Hamid; Dutt, Nikil; Ray, Sandip; Regazzoni, Francesco; Banerjee, Indranil; Cammarota, Rosario Software and Hardware Implementation of Lattice-Cased Cryptography Schemes Technical Report University of California Irvine, (CECS TR 17-04), 2017. Abstract | Links | BibTeX @techreport{2017-Hamid-TR_Survey,
title = {Software and Hardware Implementation of Lattice-Cased Cryptography Schemes},
author = {Hamid Nejatollahi and Nikil Dutt and Sandip Ray and Francesco Regazzoni and Indranil Banerjee and Rosario Cammarota},
url = {https://www.researchgate.net/publication/320963262_Software_and_Hardware_Implementation_of_Lattice-Cased_Cryptography_Schemes
http://www.cecs.uci.edu/files/2018/06/2017-tr-1.pdf
},
year = {2017},
date = {2017-01-01},
journal = {University of California Irvine, CECS TR 17-04},
number = {CECS TR 17-04},
institution = {University of California Irvine,},
abstract = {Advances in computing steadily erode computer security at its foundation, and call for fundamental innovations to strengthen current practices in computer security, specifically in applied cryptography, from theory to standardization to actual implementations. At the same time, the emergence of new computing paradigms, such as cloud computing, software defined networks and Internet of Everything, demands devices to adopt an increasing number of security standards - with a diverse set of cryptographic primitives. This in turn calls for innovations in security beyond the foundational aspects, down to the actual design and deployment of such primitives and protocols while satisfying conflicting design constraints such as latency, compactness, and energy efficiency. The advent of Quantum computing threatens to break many classical cryptographic schemes, leading to innovations in public key cryptography that focus on post-quantum cryptography primitives and their protocols that are resistant to quantum computing threats. In particular, lattice-based cryptography is a promising post-quantum cryptography family, both in terms of foundational properties, as well as its application to both traditional and emerging security problems such as encryption (asymmetric, but also symmetric), digital signature, key exchange, homomorphic encryption etc. While such techniques provide guarantees in theory, their realization on contemporary computing platforms requires careful design choices and tradeoffs to manage both the diversity of computing platforms (e.g., high-performance to resource constrained), as well as agility for deployment in the face of emerging and changing standards. In this work we survey trends in lattice-based cryptographic schemes, some fundamental recent proposals for the use of lattices in computer security, challenges for their implementation in software and hardware, and emerging needs for their adoption.},
keywords = {},
pubstate = {published},
tppubtype = {techreport}
}
Advances in computing steadily erode computer security at its foundation, and call for fundamental innovations to strengthen current practices in computer security, specifically in applied cryptography, from theory to standardization to actual implementations. At the same time, the emergence of new computing paradigms, such as cloud computing, software defined networks and Internet of Everything, demands devices to adopt an increasing number of security standards - with a diverse set of cryptographic primitives. This in turn calls for innovations in security beyond the foundational aspects, down to the actual design and deployment of such primitives and protocols while satisfying conflicting design constraints such as latency, compactness, and energy efficiency. The advent of Quantum computing threatens to break many classical cryptographic schemes, leading to innovations in public key cryptography that focus on post-quantum cryptography primitives and their protocols that are resistant to quantum computing threats. In particular, lattice-based cryptography is a promising post-quantum cryptography family, both in terms of foundational properties, as well as its application to both traditional and emerging security problems such as encryption (asymmetric, but also symmetric), digital signature, key exchange, homomorphic encryption etc. While such techniques provide guarantees in theory, their realization on contemporary computing platforms requires careful design choices and tradeoffs to manage both the diversity of computing platforms (e.g., high-performance to resource constrained), as well as agility for deployment in the face of emerging and changing standards. In this work we survey trends in lattice-based cryptographic schemes, some fundamental recent proposals for the use of lattices in computer security, challenges for their implementation in software and hardware, and emerging needs for their adoption. |
Jantsch, Axel; Dutt, Nikil D Guest Editorial: Special Issue on Self-Aware Systems on Chip Journal Article IEEE Design & Test, 34 (6), pp. 6–7, 2017. Links | BibTeX @article{DBLP:journals/dt/JantschD17,
title = {Guest Editorial: Special Issue on Self-Aware Systems on Chip},
author = {Axel Jantsch and Nikil D Dutt},
url = {https://doi.org/10.1109/MDAT.2017.2757445},
doi = {10.1109/MDAT.2017.2757445},
year = {2017},
date = {2017-01-01},
journal = {IEEE Design & Test},
volume = {34},
number = {6},
pages = {6--7},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Jantsch, Axel; Dutt, Nikil D; Rahmani, Amir M Self-Awareness in Systems on Chip - A Survey Journal Article IEEE Design & Test, 34 (6), pp. 8–26, 2017. Links | BibTeX @article{DBLP:journals/dt/JantschDR17,
title = {Self-Awareness in Systems on Chip - A Survey},
author = {Axel Jantsch and Nikil D Dutt and Amir M Rahmani},
url = {https://doi.org/10.1109/MDAT.2017.2757143},
doi = {10.1109/MDAT.2017.2757143},
year = {2017},
date = {2017-01-01},
journal = {IEEE Design & Test},
volume = {34},
number = {6},
pages = {8--26},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Shoushtari, Majid; Dutt, Nikil D SAM: Software-Assisted Memory Hierarchy for Scalable Manycore Embedded
Systems Journal Article Embedded Systems Letters, 9 (4), pp. 109–112, 2017. Links | BibTeX @article{DBLP:journals/esl/ShoushtariD17,
title = {SAM: Software-Assisted Memory Hierarchy for Scalable Manycore Embedded
Systems},
author = {Majid Shoushtari and Nikil D Dutt},
url = {https://doi.org/10.1109/LES.2017.2748098},
doi = {10.1109/LES.2017.2748098},
year = {2017},
date = {2017-01-01},
journal = {Embedded Systems Letters},
volume = {9},
number = {4},
pages = {109--112},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Azimi, Iman; Anzanpour, Arman; Rahmani, Amir M; Pahikkala, Tapio; Levorato, Marco; Liljeberg, Pasi; Dutt, Nikil D HiCH: Hierarchical Fog-Assisted Computing Architecture for Healthcare IoT Journal Article ACM Trans. Embedded Comput. Syst., 16 (5), pp. 174:1–174:20, 2017. Links | BibTeX @article{DBLP:journals/tecs/AzimiARPLLD17,
title = {HiCH: Hierarchical Fog-Assisted Computing Architecture for Healthcare IoT},
author = {Iman Azimi and Arman Anzanpour and Amir M Rahmani and Tapio Pahikkala and Marco Levorato and Pasi Liljeberg and Nikil D Dutt},
url = {http://doi.acm.org/10.1145/3126501},
doi = {10.1145/3126501},
year = {2017},
date = {2017-01-01},
journal = {ACM Trans. Embedded Comput. Syst.},
volume = {16},
number = {5},
pages = {174:1--174:20},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Mück, Tiago Rogério; Ghaderi, Zana; Dutt, Nikil D; Bozorgzadeh, Eli Exploiting Heterogeneity for Aging-Aware Load Balancing in Mobile
Platforms Journal Article IEEE Trans. Multi-Scale Computing Systems, 3 (1), pp. 25–35, 2017. Links | BibTeX @article{DBLP:journals/tmscs/MuckGDB17,
title = {Exploiting Heterogeneity for Aging-Aware Load Balancing in Mobile
Platforms},
author = {Tiago Rogério Mück and Zana Ghaderi and Nikil D Dutt and Eli Bozorgzadeh},
url = {https://doi.org/10.1109/TMSCS.2016.2627541},
doi = {10.1109/TMSCS.2016.2627541},
year = {2017},
date = {2017-01-01},
journal = {IEEE Trans. Multi-Scale Computing Systems},
volume = {3},
number = {1},
pages = {25--35},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Kanduri, Anil; Haghbayan, Mohammad Hashem; Rahmani, Amir M; Liljeberg, Pasi; Jantsch, Axel; Tenhunen, Hannu; Dutt, Nikil D Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient
Applications Journal Article IEEE Trans. VLSI Syst., 25 (10), pp. 2749–2762, 2017. Links | BibTeX @article{DBLP:journals/tvlsi/KanduriHRLJTD17,
title = {Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient
Applications},
author = {Anil Kanduri and Mohammad Hashem Haghbayan and Amir M Rahmani and Pasi Liljeberg and Axel Jantsch and Hannu Tenhunen and Nikil D Dutt},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2694388},
doi = {10.1109/TVLSI.2017.2694388},
year = {2017},
date = {2017-01-01},
journal = {IEEE Trans. VLSI Syst.},
volume = {25},
number = {10},
pages = {2749--2762},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Shoushtari, Majid; Rahmani, Amir M; Dutt, Nikil D Quality-configurable memory hierarchy through approximation: special
session Inproceedings Proceedings of the 2017 International Conference on Compilers, Architectures
and Synthesis for Embedded Systems, CASES 2017, Seoul, Republic
of Korea, October 15-20, 2017, pp. 2:1–2:2, 2017. Links | BibTeX @inproceedings{DBLP:conf/cases/ShoushtariRD17,
title = {Quality-configurable memory hierarchy through approximation: special
session},
author = {Majid Shoushtari and Amir M Rahmani and Nikil D Dutt},
url = {http://doi.acm.org/10.1145/3125501.3125525},
doi = {10.1145/3125501.3125525},
year = {2017},
date = {2017-01-01},
booktitle = {Proceedings of the 2017 International Conference on Compilers, Architectures
and Synthesis for Embedded Systems, CASES 2017, Seoul, Republic
of Korea, October 15-20, 2017},
pages = {2:1--2:2},
crossref = {DBLP:conf/cases/2017},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Donyanavard, Bryan; Monazzah, Amir Mahdi Hosseini; Mück, Tiago; Dutt, Nikil D Exploring fast and slow memories in HMP core types: work-in-progress Inproceedings Proceedings of the Twelfth IEEE/ACM/IFIP International Conference
on Hardware/Software Codesign and System Synthesis Companion, CODES+ISSS
2017, Seoul, Republic of Korea, October 15-20, 2017, pp. 4:1–4:2, 2017. Links | BibTeX @inproceedings{DBLP:conf/codes/DonyanavardMMD17,
title = {Exploring fast and slow memories in HMP core types: work-in-progress},
author = {Bryan Donyanavard and Amir Mahdi Hosseini Monazzah and Tiago Mück and Nikil D Dutt},
url = {http://doi.acm.org/10.1145/3125502.3125545},
doi = {10.1145/3125502.3125545},
year = {2017},
date = {2017-01-01},
booktitle = {Proceedings of the Twelfth IEEE/ACM/IFIP International Conference
on Hardware/Software Codesign and System Synthesis Companion, CODES+ISSS
2017, Seoul, Republic of Korea, October 15-20, 2017},
pages = {4:1--4:2},
crossref = {DBLP:conf/codes/2017},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Anzanpour, Arman; Azimi, Iman; Gotzinger, Maximilian; Rahmani, Amir M; Taherinejad, Nima; Liljeberg, Pasi; Jantsch, Axel; Dutt, Nikil D Self-awareness in remote health monitoring systems using wearable electronics Inproceedings Design, Automation & Test in Europe Conference & Exhibition,
DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 1056–1061, 2017. Links | BibTeX @inproceedings{DBLP:conf/date/AnzanpourAGRTLJ17,
title = {Self-awareness in remote health monitoring systems using wearable electronics},
author = {Arman Anzanpour and Iman Azimi and Maximilian Gotzinger and Amir M Rahmani and Nima Taherinejad and Pasi Liljeberg and Axel Jantsch and Nikil D Dutt},
url = {https://doi.org/10.23919/DATE.2017.7927146},
doi = {10.23919/DATE.2017.7927146},
year = {2017},
date = {2017-01-01},
booktitle = {Design, Automation & Test in Europe Conference & Exhibition,
DATE 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {1056--1061},
crossref = {DBLP:conf/date/2017},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Park, Jurn-Gyu; Dutt, Nikil D; Lim, Sung-Soo ML-Gov: a machine learning enhanced integrated CPU-GPU DVFS governor
for mobile gaming Inproceedings Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for
Real-Time Multimedia, ESTImedia 2017, Seoul, Republic of Korea, October
15 - 20, 2017, pp. 12–21, 2017. Links | BibTeX @inproceedings{DBLP:conf/estimedia/ParkDL17,
title = {ML-Gov: a machine learning enhanced integrated CPU-GPU DVFS governor
for mobile gaming},
author = {Jurn-Gyu Park and Nikil D Dutt and Sung-Soo Lim},
url = {http://doi.acm.org/10.1145/3139315.3139317},
doi = {10.1145/3139315.3139317},
year = {2017},
date = {2017-01-01},
booktitle = {Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for
Real-Time Multimedia, ESTImedia 2017, Seoul, Republic of Korea, October
15 - 20, 2017},
pages = {12--21},
crossref = {DBLP:conf/estimedia/2017},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Monazzah, Amir Mahdi Hosseini; Shoushtari, Majid; Miremadi, Seyed Ghassem; Rahmani, Amir M; Dutt, Nikil D QuARK: Quality-configurable approximate STT-MRAM cache by fine-grained
tuning of reliability-energy knobs Inproceedings 2017 IEEE/ACM International Symposium on Low Power Electronics and
Design, ISLPED 2017, Taipei, Taiwan, July 24-26, 2017, pp. 1–6, 2017. Links | BibTeX @inproceedings{DBLP:conf/islped/MonazzahSMRD17,
title = {QuARK: Quality-configurable approximate STT-MRAM cache by fine-grained
tuning of reliability-energy knobs},
author = {Amir Mahdi Hosseini Monazzah and Majid Shoushtari and Seyed Ghassem Miremadi and Amir M Rahmani and Nikil D Dutt},
url = {https://doi.org/10.1109/ISLPED.2017.8009198},
doi = {10.1109/ISLPED.2017.8009198},
year = {2017},
date = {2017-01-01},
booktitle = {2017 IEEE/ACM International Symposium on Low Power Electronics and
Design, ISLPED 2017, Taipei, Taiwan, July 24-26, 2017},
pages = {1--6},
crossref = {DBLP:conf/islped/2017},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Aliee, Hananeh; BanaiyanMofrad, Abbas; ß, Michael Gla; ü, J; Dutt, Nikil D Redundancy-aware Design Space Exploration for Memory Reliability in
Many-cores Inproceedings Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February
8-9, 2017., pp. 1–12, 2017. BibTeX @inproceedings{DBLP:conf/mbmv/AlieeBGTD17,
title = {Redundancy-aware Design Space Exploration for Memory Reliability in
Many-cores},
author = {Hananeh Aliee and Abbas BanaiyanMofrad and Michael Gla ß and J ü and Nikil D Dutt},
year = {2017},
date = {2017-01-01},
booktitle = {Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February
8-9, 2017.},
pages = {1--12},
crossref = {DBLP:conf/mbmv/2017},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Dutt, Nikil D; Rahmani, Amir M; Jantsch, Axel Empowering autonomy through self-awareness in MPSoCs Inproceedings 15th IEEE International New Circuits and Systems Conference, NEWCAS
2017, Strasbourg, France, June 25-28, 2017, pp. 73–76, 2017. Links | BibTeX @inproceedings{DBLP:conf/newcas/DuttRJ17,
title = {Empowering autonomy through self-awareness in MPSoCs},
author = {Nikil D Dutt and Amir M Rahmani and Axel Jantsch},
url = {https://doi.org/10.1109/NEWCAS.2017.8010108},
doi = {10.1109/NEWCAS.2017.8010108},
year = {2017},
date = {2017-01-01},
booktitle = {15th IEEE International New Circuits and Systems Conference, NEWCAS
2017, Strasbourg, France, June 25-28, 2017},
pages = {73--76},
crossref = {DBLP:conf/newcas/2017},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Shahosseini, Sina; Moazzemi, Kasra; Rahmani, Amir M; Dutt, Nikil D Dependability evaluation of SISO control-theoretic power managers for processor architectures Inproceedings IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP
and International Symposium of System-on-Chip (SoC), Linköping,
Sweden, October 23-25, 2017, pp. 1–6, 2017. Links | BibTeX @inproceedings{DBLP:conf/norchip/ShahosseiniMRD17,
title = {Dependability evaluation of SISO control-theoretic power managers for processor architectures},
author = {Sina Shahosseini and Kasra Moazzemi and Amir M Rahmani and Nikil D Dutt},
url = {http://duttgroup.ics.uci.edu/wp-content/drg/uploads/2018/05/NORCAS_drg.pdf
https://doi.org/10.1109/NORCHIP.2017.8124983},
doi = {10.1109/NORCHIP.2017.8124983},
year = {2017},
date = {2017-01-01},
booktitle = {IEEE Nordic Circuits and Systems Conference, NORCAS 2017: NORCHIP
and International Symposium of System-on-Chip (SoC), Linköping,
Sweden, October 23-25, 2017},
pages = {1--6},
crossref = {DBLP:conf/norchip/2017},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Mück, Tiago; Donyanavard, Bryan; Dutt, Nikil D PoIiCym: rapid prototyping of resource management policies for HMPs Inproceedings International Symposium on Rapid System Prototyping, RSP 2017, Shortening
the Path from Specification to Prototype, October 19-20, 2017, Seoul,
South Korea., pp. 23–29, 2017. Links | BibTeX @inproceedings{DBLP:conf/rsp/MuckDD17,
title = {PoIiCym: rapid prototyping of resource management policies for HMPs},
author = {Tiago Mück and Bryan Donyanavard and Nikil D Dutt},
url = {http://doi.acm.org/10.1145/3130265.3130321},
doi = {10.1145/3130265.3130321},
year = {2017},
date = {2017-01-01},
booktitle = {International Symposium on Rapid System Prototyping, RSP 2017, Shortening
the Path from Specification to Prototype, October 19-20, 2017, Seoul,
South Korea.},
pages = {23--29},
crossref = {DBLP:conf/rsp/2017},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Das, Anup; Pradhapan, Paruthi; Groenendaal, Willemijn; Adiraju, Prathyusha; Rajan, Raj Thilak; Catthoor, Francky; Schaafsma, Siebren; Krichmar, Jeffrey L; Dutt, Nikil D; Hoof, Chris Van Unsupervised Heart-rate Estimation in Wearables With Liquid States
and A Probabilistic Readout Journal Article CoRR, abs/1708.05356 , 2017. Links | BibTeX @article{DBLP:journals/corr/abs-1708-05356,
title = {Unsupervised Heart-rate Estimation in Wearables With Liquid States
and A Probabilistic Readout},
author = {Anup Das and Paruthi Pradhapan and Willemijn Groenendaal and Prathyusha Adiraju and Raj Thilak Rajan and Francky Catthoor and Siebren Schaafsma and Jeffrey L Krichmar and Nikil D Dutt and Chris Van Hoof},
url = {http://arxiv.org/abs/1708.05356},
year = {2017},
date = {2017-01-01},
journal = {CoRR},
volume = {abs/1708.05356},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Detorakis, Georgios; Sheik, Sadique; Augustine, Charles; Paul, Somnath; Pedroni, Bruno U; Dutt, Nikil D; Krichmar, Jeffrey L; Cauwenberghs, Gert; Neftci, Emre Neural and Synaptic Array Transceiver: A Brain-Inspired Computing
Framework for Embedded Learning Journal Article CoRR, abs/1709.10205 , 2017. Links | BibTeX @article{DBLP:journals/corr/abs-1709-10205,
title = {Neural and Synaptic Array Transceiver: A Brain-Inspired Computing
Framework for Embedded Learning},
author = {Georgios Detorakis and Sadique Sheik and Charles Augustine and Somnath Paul and Bruno U Pedroni and Nikil D Dutt and Jeffrey L Krichmar and Gert Cauwenberghs and Emre Neftci},
url = {http://arxiv.org/abs/1709.10205},
year = {2017},
date = {2017-01-01},
journal = {CoRR},
volume = {abs/1709.10205},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
2016
|
Shrivastava, Aviral; Dutt, Nikil D; Cai, Jian; Shoushtari, Majid; Donyanavard, Bryan; Tajik, Hossein Automatic management of Software Programmable Memories in Many-core
Architectures Journal Article IET Computers & Digital Techniques, 10 (6), pp. 288–298, 2016. Links | BibTeX @article{DBLP:journals/iet-cdt/ShrivastavaDCSD16,
title = {Automatic management of Software Programmable Memories in Many-core
Architectures},
author = {Aviral Shrivastava and Nikil D Dutt and Jian Cai and Majid Shoushtari and Bryan Donyanavard and Hossein Tajik},
url = {https://doi.org/10.1049/iet-cdt.2016.0024},
doi = {10.1049/iet-cdt.2016.0024},
year = {2016},
date = {2016-01-01},
journal = {IET Computers & Digital Techniques},
volume = {10},
number = {6},
pages = {288--298},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Dutt, Nikil D; Jantsch, Axel; Sarma, Santanu Toward Smart Embedded Systems: A Self-aware System-on-Chip (SoC)
Perspective Journal Article ACM Trans. Embedded Comput. Syst., 15 (2), pp. 22:1–22:27, 2016. Links | BibTeX @article{DBLP:journals/tecs/DuttJS16,
title = {Toward Smart Embedded Systems: A Self-aware System-on-Chip (SoC)
Perspective},
author = {Nikil D Dutt and Axel Jantsch and Santanu Sarma},
url = {http://doi.acm.org/10.1145/2872936},
doi = {10.1145/2872936},
year = {2016},
date = {2016-01-01},
journal = {ACM Trans. Embedded Comput. Syst.},
volume = {15},
number = {2},
pages = {22:1--22:27},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Tajik, Hossein; Donyanavard, Bryan; Dutt, Nikil D; Jahn, Janmartin; ö, J SPMPool: Runtime SPM Management for Memory-Intensive Applications
in Embedded Many-Cores Journal Article ACM Trans. Embedded Comput. Syst., 16 (1), pp. 25:1–25:27, 2016. Links | BibTeX @article{DBLP:journals/tecs/TajikDDJH16,
title = {SPMPool: Runtime SPM Management for Memory-Intensive Applications
in Embedded Many-Cores},
author = {Hossein Tajik and Bryan Donyanavard and Nikil D Dutt and Janmartin Jahn and J ö},
url = {http://dl.acm.org/citation.cfm?id=2968447},
year = {2016},
date = {2016-01-01},
journal = {ACM Trans. Embedded Comput. Syst.},
volume = {16},
number = {1},
pages = {25:1--25:27},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Sarma, Santanu; Mück, Tiago; Shoushtari, Majid; BanaiyanMofrad, Abbas; Dutt, Nikil D Cross-layer virtual/physical sensing and actuation for resilient heterogeneous
many-core SoCs Inproceedings 21st Asia and South Pacific Design Automation Conference, ASP-DAC
2016, Macao, Macao, January 25-28, 2016, pp. 395–402, 2016. Links | BibTeX @inproceedings{DBLP:conf/aspdac/SarmaMSBD16,
title = {Cross-layer virtual/physical sensing and actuation for resilient heterogeneous
many-core SoCs},
author = {Santanu Sarma and Tiago Mück and Majid Shoushtari and Abbas BanaiyanMofrad and Nikil D Dutt},
url = {https://doi.org/10.1109/ASPDAC.2016.7428044},
doi = {10.1109/ASPDAC.2016.7428044},
year = {2016},
date = {2016-01-01},
booktitle = {21st Asia and South Pacific Design Automation Conference, ASP-DAC
2016, Macao, Macao, January 25-28, 2016},
pages = {395--402},
crossref = {DBLP:conf/aspdac/2016},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Donyanavard, Bryan; Mück, Tiago; Sarma, Santanu; Dutt, Nikil D SPARTA: runtime task allocation for energy efficient heterogeneous many-cores Inproceedings Proceedings of the Eleventh IEEE/ACM/IFIP International Conference
on Hardware/Software Codesign and System Synthesis, CODES 2016,
Pittsburgh, Pennsylvania, USA, October 1-7, 2016, pp. 27:1–27:10, 2016. Links | BibTeX @inproceedings{DBLP:conf/codes/DonyanavardMSD16,
title = {SPARTA: runtime task allocation for energy efficient heterogeneous many-cores},
author = {Bryan Donyanavard and Tiago Mück and Santanu Sarma and Nikil D Dutt},
url = {http://doi.acm.org/10.1145/2968456.2968459},
doi = {10.1145/2968456.2968459},
year = {2016},
date = {2016-01-01},
booktitle = {Proceedings of the Eleventh IEEE/ACM/IFIP International Conference
on Hardware/Software Codesign and System Synthesis, CODES 2016,
Pittsburgh, Pennsylvania, USA, October 1-7, 2016},
pages = {27:1--27:10},
crossref = {DBLP:conf/codes/2016},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Dutt, Nikil D; Kurdahi, Fadi J; Ernst, Rolf; Herkersdorf, Andreas Conquering MPSoC complexity with principles of a self-aware information
processing factory Inproceedings Proceedings of the Eleventh IEEE/ACM/IFIP International Conference
on Hardware/Software Codesign and System Synthesis, CODES 2016,
Pittsburgh, Pennsylvania, USA, October 1-7, 2016, pp. 37:1–37:4, 2016. Links | BibTeX @inproceedings{DBLP:conf/codes/DuttKEH16,
title = {Conquering MPSoC complexity with principles of a self-aware information
processing factory},
author = {Nikil D Dutt and Fadi J Kurdahi and Rolf Ernst and Andreas Herkersdorf},
url = {http://doi.acm.org/10.1145/2968456.2973275},
doi = {10.1145/2968456.2973275},
year = {2016},
date = {2016-01-01},
booktitle = {Proceedings of the Eleventh IEEE/ACM/IFIP International Conference
on Hardware/Software Codesign and System Synthesis, CODES 2016,
Pittsburgh, Pennsylvania, USA, October 1-7, 2016},
pages = {37:1--37:4},
crossref = {DBLP:conf/codes/2016},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Tajik, Hossein; Donyanavard, Bryan; Dutt, Nikil D On Detecting and Using Memory Phases in Multimedia Systems Inproceedings Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for
Real-Time Multimedia, ESTIMedia 2016, Pittsburgh, PA, USA, October
6-7, 2016, pp. 57–66, 2016. Links | BibTeX @inproceedings{DBLP:conf/estimedia/TajikDD16,
title = {On Detecting and Using Memory Phases in Multimedia Systems},
author = {Hossein Tajik and Bryan Donyanavard and Nikil D Dutt},
url = {http://dl.acm.org/citation.cfm?id=2993566},
year = {2016},
date = {2016-01-01},
booktitle = {Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for
Real-Time Multimedia, ESTIMedia 2016, Pittsburgh, PA, USA, October
6-7, 2016},
pages = {57--66},
crossref = {DBLP:conf/estimedia/2016},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Kanduri, Anil; Haghbayan, Mohammad Hashem; Rahmani, Amir-Mohammad; Liljeberg, Pasi; Jantsch, Axel; Dutt, Nikil D; Tenhunen, Hannu Approximation knob: power capping meets energy efficiency Inproceedings Proceedings of the 35th International Conference on Computer-Aided
Design, ICCAD 2016, Austin, TX, USA, November 7-10, 2016, pp. 122, 2016. Links | BibTeX @inproceedings{DBLP:conf/iccad/KanduriHRLJDT16,
title = {Approximation knob: power capping meets energy efficiency},
author = {Anil Kanduri and Mohammad Hashem Haghbayan and Amir-Mohammad Rahmani and Pasi Liljeberg and Axel Jantsch and Nikil D Dutt and Hannu Tenhunen},
url = {http://doi.acm.org/10.1145/2966986.2967002},
doi = {10.1145/2966986.2967002},
year = {2016},
date = {2016-01-01},
booktitle = {Proceedings of the 35th International Conference on Computer-Aided
Design, ICCAD 2016, Austin, TX, USA, November 7-10, 2016},
pages = {122},
crossref = {DBLP:conf/iccad/2016},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Park, Jurn-Gyu; Dutt, Nikil D; Kim, Hoyeonjiki; Lim, Sung-Soo HiCAP: Hierarchical FSM-based Dynamic Integrated CPU-GPU Frequency
Capping Governor for Energy-Efficient Mobile Gaming Inproceedings Proceedings of the 2016 International Symposium on Low Power Electronics
and Design, ISLPED 2016, San Francisco Airport, CA, USA, August
08 - 10, 2016, pp. 218–223, 2016. Links | BibTeX @inproceedings{DBLP:conf/islped/ParkDKL16,
title = {HiCAP: Hierarchical FSM-based Dynamic Integrated CPU-GPU Frequency
Capping Governor for Energy-Efficient Mobile Gaming},
author = {Jurn-Gyu Park and Nikil D Dutt and Hoyeonjiki Kim and Sung-Soo Lim},
url = {http://doi.acm.org/10.1145/2934583.2934588},
doi = {10.1145/2934583.2934588},
year = {2016},
date = {2016-01-01},
booktitle = {Proceedings of the 2016 International Symposium on Low Power Electronics
and Design, ISLPED 2016, San Francisco Airport, CA, USA, August
08 - 10, 2016},
pages = {218--223},
crossref = {DBLP:conf/islped/2016},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Moazzemi, Kasra; Hsieh, Chen-Ying; Dutt, Nikil D HAMEX: heterogeneous architecture and memory exploration framework Inproceedings 2016 International Symposium on Rapid System Prototyping, RSP 2016,
Pittsburg, PA, USA, October 6-7, 2016, pp. 100–106, 2016. Links | BibTeX @inproceedings{DBLP:conf/rsp/MoazzemiHD16,
title = {HAMEX: heterogeneous architecture and memory exploration framework},
author = {Kasra Moazzemi and Chen-Ying Hsieh and Nikil D Dutt},
url = {https://doi.org/10.1145/2990299.2990316},
doi = {10.1145/2990299.2990316},
year = {2016},
date = {2016-01-01},
booktitle = {2016 International Symposium on Rapid System Prototyping, RSP 2016,
Pittsburg, PA, USA, October 6-7, 2016},
pages = {100--106},
crossref = {DBLP:conf/rsp/2016},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Park, Jurn-Gyu; Hsieh, Chen-Ying; Dutt, Nikil D; Lim, Sung-Soo Co-Cap: energy-efficient cooperative CPU-GPU frequency capping for
mobile games Inproceedings Proceedings of the 31st Annual ACM Symposium on Applied Computing,
Pisa, Italy, April 4-8, 2016, pp. 1717–1723, 2016. Links | BibTeX @inproceedings{DBLP:conf/sac/ParkHDL16,
title = {Co-Cap: energy-efficient cooperative CPU-GPU frequency capping for
mobile games},
author = {Jurn-Gyu Park and Chen-Ying Hsieh and Nikil D Dutt and Sung-Soo Lim},
url = {http://doi.acm.org/10.1145/2851613.2851671},
doi = {10.1145/2851613.2851671},
year = {2016},
date = {2016-01-01},
booktitle = {Proceedings of the 31st Annual ACM Symposium on Applied Computing,
Pisa, Italy, April 4-8, 2016},
pages = {1717--1723},
crossref = {DBLP:conf/sac/2016},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
Dutt, Nikil D; Taherinejad, Nima Self-Awareness in Cyber-Physical Systems Inproceedings 29th International Conference on VLSI Design and 15th International
Conference on Embedded Systems, VLSID 2016, Kolkata, India, January
4-8, 2016, pp. 5–6, 2016. Links | BibTeX @inproceedings{DBLP:conf/vlsid/DuttT16,
title = {Self-Awareness in Cyber-Physical Systems},
author = {Nikil D Dutt and Nima Taherinejad},
url = {https://doi.org/10.1109/VLSID.2016.129},
doi = {10.1109/VLSID.2016.129},
year = {2016},
date = {2016-01-01},
booktitle = {29th International Conference on VLSI Design and 15th International
Conference on Embedded Systems, VLSID 2016, Kolkata, India, January
4-8, 2016},
pages = {5--6},
crossref = {DBLP:conf/vlsid/2016},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
2015
|
Shoushtari, Majid; BanaiyanMofrad, Abbas; Dutt, Nikil D Exploiting Partially-Forgetful Memories for Approximate Computing Journal Article Embedded Systems Letters, 7 (1), pp. 19–22, 2015. Links | BibTeX @article{DBLP:journals/esl/ShoushtariBD15,
title = {Exploiting Partially-Forgetful Memories for Approximate Computing},
author = {Majid Shoushtari and Abbas BanaiyanMofrad and Nikil D Dutt},
url = {https://doi.org/10.1109/LES.2015.2393860},
doi = {10.1109/LES.2015.2393860},
year = {2015},
date = {2015-01-01},
journal = {Embedded Systems Letters},
volume = {7},
number = {1},
pages = {19--22},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Shin, Jun Yong; Kurdahi, Fadi J; Dutt, Nikil D Cooperative On-Chip Temperature EstimationUsing Multiple Virtual Sensors Journal Article Embedded Systems Letters, 7 (2), pp. 37–40, 2015. Links | BibTeX @article{DBLP:journals/esl/ShinKD15,
title = {Cooperative On-Chip Temperature EstimationUsing Multiple Virtual Sensors},
author = {Jun Yong Shin and Fadi J Kurdahi and Nikil D Dutt},
url = {https://doi.org/10.1109/LES.2015.2400992},
doi = {10.1109/LES.2015.2400992},
year = {2015},
date = {2015-01-01},
journal = {Embedded Systems Letters},
volume = {7},
number = {2},
pages = {37--40},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Wanner, Lucas Francisco; Lai, Liangzhen; Rahimi, Abbas; Gottscho, Mark; Mercati, Pietro; Huang, Chu-Hsiang; Sala, Frederic; Agarwal, Yuvraj; Dolecek, Lara; Dutt, Nikil D; Gupta, Puneet; Gupta, Rajesh K; Jhala, Ranjit; Kumar, Rakesh; Lerner, Sorin; Mitra, Subhasish; Nicolau, Alexandru; Rosing, Tajana Simunic; Srivastava, Mani B; Swanson, Steven; Sylvester, Dennis; Zhou, Yuanyuan NSF expedition on variability-aware software: Recent results and
contributions Journal Article it - Information Technology, 57 (3), pp. 181–198, 2015. Links | BibTeX @article{DBLP:journals/it/WannerLRGMHSADD15,
title = {NSF expedition on variability-aware software: Recent results and
contributions},
author = {Lucas Francisco Wanner and Liangzhen Lai and Abbas Rahimi and Mark Gottscho and Pietro Mercati and Chu-Hsiang Huang and Frederic Sala and Yuvraj Agarwal and Lara Dolecek and Nikil D Dutt and Puneet Gupta and Rajesh K Gupta and Ranjit Jhala and Rakesh Kumar and Sorin Lerner and Subhasish Mitra and Alexandru Nicolau and Tajana Simunic Rosing and Mani B Srivastava and Steven Swanson and Dennis Sylvester and Yuanyuan Zhou},
url = {https://doi.org/10.1515/itit-2014-1085},
doi = {10.1515/itit-2014-1085},
year = {2015},
date = {2015-01-01},
journal = {it - Information Technology},
volume = {57},
number = {3},
pages = {181--198},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Krichmar, Jeffrey L; Coussy, Philippe; Dutt, Nikil D Large-Scale Spiking Neural Networks using Neuromorphic Hardware Compatible
Models Journal Article JETC, 11 (4), pp. 36:1–36:18, 2015. Links | BibTeX @article{DBLP:journals/jetc/KrichmarCD15,
title = {Large-Scale Spiking Neural Networks using Neuromorphic Hardware Compatible
Models},
author = {Jeffrey L Krichmar and Philippe Coussy and Nikil D Dutt},
url = {http://doi.acm.org/10.1145/2629509},
doi = {10.1145/2629509},
year = {2015},
date = {2015-01-01},
journal = {JETC},
volume = {11},
number = {4},
pages = {36:1--36:18},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Beyeler, Michael; Oros, Nicolas; Dutt, Nikil D; Krichmar, Jeffrey L A GPU-accelerated cortical neural network model for visually guided
robot navigation Journal Article Neural Networks, 72 , pp. 75–87, 2015. Links | BibTeX @article{DBLP:journals/nn/BeyelerODK15,
title = {A GPU-accelerated cortical neural network model for visually guided
robot navigation},
author = {Michael Beyeler and Nicolas Oros and Nikil D Dutt and Jeffrey L Krichmar},
url = {https://doi.org/10.1016/j.neunet.2015.09.005},
doi = {10.1016/j.neunet.2015.09.005},
year = {2015},
date = {2015-01-01},
journal = {Neural Networks},
volume = {72},
pages = {75--87},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|
Gottscho, Mark; BanaiyanMofrad, Abbas; Dutt, Nikil D; Nicolau, Alex; Gupta, Puneet DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale
Era Journal Article TACO, 12 (3), pp. 27:1–27:26, 2015. Links | BibTeX @article{DBLP:journals/taco/GottschoBDNG15,
title = {DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale
Era},
author = {Mark Gottscho and Abbas BanaiyanMofrad and Nikil D Dutt and Alex Nicolau and Puneet Gupta},
url = {http://doi.acm.org/10.1145/2792982},
doi = {10.1145/2792982},
year = {2015},
date = {2015-01-01},
journal = {TACO},
volume = {12},
number = {3},
pages = {27:1--27:26},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
|